Generally, a microprocessor of an electronic device continues to burn power even when the device is idle and the microprocessor is in sleep or hibernation mode, as a result of leakage currents flowing through the transistors of the microprocessor. Power to the transistors cannot be turned off entirely at sleep mode due to the existence of latches/flops and SRAMs in a volatile (data) charge based processor. While generally undesirable, power leakage is even more important in mobile devices where idle time may be long and battery life is of critical importance.
As leakage power scales with supply voltage, power leakage during idle periods may be reduced by lowering the supply voltage to the minimum voltage required for data retention known as Vccmin. However, as Vccmin is non-zero, and may, in some technologies, be about 0.4 V to about 0.5 V, current leakage persists. Other methods for mitigating this leakage problem may include using volatile shadow latches/circuits constructed with low leakage devices to lower leakage, or transferring most of the volatile data to the non-volatile RAM or storage during sleep mode. However, these approaches lead to very complicated circuits and long wake-up periods as data needs to be properly transferred back to the processor devices/latches/SRAMs. A further approach may involve the implementation of ferroelectric storage adjacent to the volatile storage element. However, even in this approach, the storage media still burns substantial dynamic power.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art.